Freescale Semiconductor /MK60D10 /ADC0 /CFG2

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CFG2

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (00)ADLSTS 0 (0)ADHSC 0 (0)ADACKEN 0 (0)MUXSEL

ADACKEN=0, MUXSEL=0, ADLSTS=00, ADHSC=0

Description

ADC Configuration Register 2

Fields

ADLSTS

Long Sample Time Select

0 (00): Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles total.

1 (01): 12 extra ADCK cycles; 16 ADCK cycles total sample time.

2 (10): 6 extra ADCK cycles; 10 ADCK cycles total sample time.

3 (11): 2 extra ADCK cycles; 6 ADCK cycles total sample time.

ADHSC

High-Speed Configuration

0 (0): Normal conversion sequence selected.

1 (1): High-speed conversion sequence selected with 2 additional ADCK cycles to total conversion time.

ADACKEN

Asynchronous Clock Output Enable

0 (0): Asynchronous clock output disabled; Asynchronous clock is enabled only if selected by ADICLK and a conversion is active.

1 (1): Asynchronous clock and clock output is enabled regardless of the state of the ADC.

MUXSEL

ADC Mux Select

0 (0): ADxxa channels are selected.

1 (1): ADxxb channels are selected.

Links

() ()